So I decided to play around with the AD633 analogue multiplier in PSPICE to get some idea if it was any good.
First problem: find a model. Ah yes, there's one on the Analog Devices website... (click on search results link) (get the Analog Devices page - it has uncollapsed "collapsing" menus all over it and the content area is completely blank) (inspect the DOM and verify that there is indeed no content and it's not just hidden in some stupid way) ...fucksake what kind of mindless fucking imbecile writes this shit? (Note to any mindless fucking imbeciles who might read this: (1) Make the default state of "collapsing" menus fucking collapsed; (2) Use CSS :hover selectors to make them appear, not six megabytes of shit javascript that never even fucking works anyway. You cunts.)
Back to search results... here's one on the PSPICE website... oh bollocks, but the link target is on Analog Devices's website again. And clicking it redirects to some stupid bastard clickthrough license agreement which doesn't even fucking work. I guess the mindless fucking imbecile has assumed you can set cookies. This assumption is false. Can't be arsed to debug it, so...
Back to the search engine again and since I now do at least know that I'm looking for something called "ad633.cir" or similar, I quickly find multiple copies of it on lots of different websites which do work and don't fuck me around with shit that doesn't work. And it is the genuine article.
RIGHT. Thank you Lord. Now to try it out. Bash out a netlist for the first sample circuit in the datasheet. Do a DC sweep on the inputs. Or, rather, try to. But it fails to calculate the bias point, due to fucking convergence errors.
Looking at the simulator's textual output, the errors appear to be deep within the model itself. And the sample circuit is so fucking simple that there's pretty much nothing to tweak: literally just the chip itself and some voltage sources driving the inputs. The "make it more realistic" trick of adding suitable representations of parasitic resistances does not work - it just infuriatingly appears to for a limited subset of input conditions, then you change the inputs a bit and once again all you get is fucking convergence errors.
The simulation section in the datasheet does mention that the simulation is likely to give fucking convergence errors. But it says not a bleeding thing about what to do about it. It just shows screenshots of simulations of the same fucking circuit only it works when they do it. Maybe they set different options. But they don't show the actual deck, only screenshots of some GUI front end*, so if they have fuck knows what they are. Fucking wankers.
So poking around online I discovered that not only did this model piss loads of other people off too, one of them was having the exact same problem. And down near the bottom of the page, some Italian called "Guest" had what was actually a proper solution - not just tweaking settings to try and get around the problem, but making the thing stop misbehaving in the first place.
Replace two Epoly sources with Gpoly sources in the model of the AD633. A suggestion (from "analogspiceman"):
gEOSX 10 1 POLY(1) (16,100) (5E-3,1) ; changed from E to G source with
reosx 10 1 1 ; 1 ohm across it to maintain gain
gEOSY 20 3 POLY(1) (26,100) (5E-3,1) ; changed from E to G source with
reosy 20 3 1
And this... nearly worked. It was fine until I tried to simulate the current-output configuration, then I was back to fucking convergence errors. But the suggestion that controlled voltage sources might be misbehaving and you could get around it by using a controlled current source across a resistance instead was a useful hint to look for other misbehaving controlled voltage sources, and I found that doing the same thing (suitably adjusted for context; see below) to one in the op-amp frequency response department got things going again.
Of course, it may still not be a complete solution; there is still a significant possibility that I will happen on some other combination of operating conditions that still gives fucking convergence errors. But if I do, yet another misbehaving controlled voltage source would seem to be the obvious thing to look for first. (Or, possibly, a misbehaving controlled current source that needs the reverse version of the same trick doing on it.)
*When I say "PSPICE", I mean version 5. For DOS. Which I use precisely because it does not have a GUI front end. It has a purely textual one (apart from the actual output plots, of course), and it is bloody good. I went through several emulators/VMs trying to find one that would handle the DOS extender it uses without crashing and emulate a VGA card it understood how to talk to, and ended up hacking QEMU to not crash as the easiest solution. It was that or write a Linux clone of the UI to work with ngspice - and that latter would still leave me with the problem that ngspice seems to be somewhat more liable to fucking convergence errors.
AD633 datasheet
AD633 SPICE model (modified as above)
* AD633 Analog Multiplier Macro Model * (Commented-out values are for AD633J variant) * Node assignments * X1 * | X2 * | | Y1 * | | | Y2 * | | | | VNEG * | | | | | Z * | | | | | | W * | | | | | | | VPOS * | | | | | | | | .SUBCKT AD633 1 2 3 4 5 6 7 8 * EREF 100 0 POLY(2) 8 0 5 0 (0,0.5,0.5) * * X-INPUT STAGE & POLE AT 15 MHz * IBX1 1 0 DC 8e-7 ;2E-6 IBX2 2 0 DC 8e-7 ;2E-6 * (orig: EOSX 10 1 POLY(1) (16,100) (30E-3,1) and no Rgosx) GOSX 10 1 POLY(1) (16,100) (5E-3,1) ;(30E-3,1) Rgosx 10 1 1 RX1A 10 11 5E6 RX1B 11 2 5E6 * GX 100 12 10 2 1E-6 RX 12 100 1E6 CX 12 100 1.061E-14 VX1 8 13 DC 3.05 DX1 12 13 DX VX2 14 5 DC 3.05 DX2 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz * ECMX 15 100 11 100 10 RCMX1 15 16 1E6 CCMX 15 16 2.8421E-10 RCMX2 16 100 1 * * Y-INPUT STAGE & POLE AT 15 MHz * IBY1 3 0 DC 8e-7 ;2E-6 IBY2 4 0 DC 8e-7 ;2E-6 * (orig: EOSY 20 3 POLY(1) (26,100) (30E-3,1) and no Rgosy) GOSY 20 3 POLY(1) (26,100) (5E-3,1) ;(30E-3,1) Rgosy 20 3 1 RY1A 20 21 5E6 RY1B 21 4 5E6 * GY 100 22 20 4 1E-6 RY 22 100 1E6 CY 22 100 1.061E-14 VY1 8 23 DC 3.05 DY1 22 23 DX VY2 24 5 DC 3.05 DY2 24 22 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz * ECMY 25 100 21 100 10 RCMY1 25 26 1E6 CCMY 25 26 2.8421E-10 RCMY2 26 100 1 * * Z-INPUT STAGE & POLE AT 15 MHz * IBZ1 7 0 DC 8E-7 IBZ2 6 0 DC 8E-7 RZ1 7 6 10E6 * GZ 100 32 7 6 1E-6 RZ2 32 100 1E6 CZ 32 100 1.061E-14 VZ1 8 33 DC 3.05 DZ1 32 33 DX VZ2 34 5 DC 3.05 DZ2 34 33 DX * * 50-MHz MULTIPLIER CORE & SUMMER * GXY 100 40 POLY(2) (12,100) (22,100) (0,0,0,0,0.1E-6) RXY 40 100 1E6 CXY 40 100 3.1831E-15 * * OP AMP INPUT STAGE * VOOS 59 40 DC 50E-3 Q1 55 32 60 QX Q2 56 59 61 QX R1 8 55 3.1831E4 R2 60 54 3.1313E4 R3 8 56 3.1831E4 R4 61 54 3.1313E4 I1 54 5 1E-4 * * GAIN STAGE & DOMINANT POLE AT 316.23 Hz * G1 100 62 55 56 3.141637E-5 R5 62 100 1.0066E8 C3 62 100 5E-12 V1 8 63 DC 4.3399 D1 62 63 DX V2 64 5 DC 4.3399 D2 64 62 DX * * NEGATIVE ZERO AT 20 MHz * ENZ 65 100 62 100 1E6 RNZ1 65 66 1 FNZ 65 66 VNC -1 RNZ2 66 100 1E-6 * (orig: ENC 67 0 65 66 1 and no Rgnc) GNC 67 0 65 66 10k Rgnc 67 0 0.1m CNZ 67 68 7.9577E-9 VNC 68 0 DC 0 * * POLE AT 4 MHz * G2 100 69 66 100 1E-6 R6 69 100 1E6 C2 69 100 3.9789E-14 * * OP AMP OUTPUT STAGE * FSY 8 5 POLY(2) VZC1 VZC2 (2.8286e-3,1,1) ;(4.8286E-3,1,1) RDC 8 5 28E3 GZC 100 73 72 69 11.623E-3 VZC1 74 100 DC 0 DZC1 73 74 DX VZC2 100 75 DC 0 DZC2 75 73 DX VSC1 70 72 0.695 ;1.125 DSC1 69 70 DX VSC2 72 71 0.695 ;1.125 DSC2 71 69 DX GO1 72 8 8 69 11.623E-3 RO1 8 72 86 GO2 5 72 69 5 11.623E-3 RO2 72 5 86 LO 72 7 1E-7 * * MODELS USED * .MODEL QX NPN(BF=1E4) .MODEL DX D(IS=1E-15) .ENDS
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